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LTC2420CS8 Datasheet(PDF) 13 Page - Linear Technology |
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LTC2420CS8 Datasheet(HTML) 13 Page - Linear Technology |
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13 / 36 page  13 LTC2420 APPLICATIO S I FOR ATIO Table 2. LTC2420 Output Data Format Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0 Input Voltage EOC DMY SIG EXR MSB LSB VIN > 9/8 • VREF 0 0 1100 0 11... 1 9/8 • VREF 0 0 1100 0 11... 1 VREF + 1LSB 0 0 1100 0 00... 0 VREF 0 0 1011 1 11... 1 3/4VREF + 1LSB 0 0 1011 0 00... 0 3/4VREF 0 0 1010 1 11... 1 1/2VREF + 1LSB 0 0 1010 0 00... 0 1/2VREF 0 0 1001 1 11... 1 1/4VREF + 1LSB 0 0 1001 0 00... 0 1/4VREF 0 0 1000 1 11... 1 0+/0– 0 0 1/0* 000 0 00... 0 –1LSB 0 0 0111 1 11... 1 –1/8 • VREF 0 0 0111 1 00... 0 VIN < –1/8 • VREF 0 0 0111 1 00... 0 *The sign bit changes state during the 0 code. the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the VIN pin is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from – 0.125 • VREF to 1.125 • VREF. For input voltages greater than 1.125 • VREF, the conversion result is clamped to the value corresponding to 1.125 • VREF. For input voltages below – 0.125 • VREF, the conversion result is clamped to the value corresponding to – 0.125 • VREF. Frequency Rejection Selection (FO Pin Connection) The LTC2420 internal oscillator provides better than 110dB normal mode rejection at the line frequency and its har- monics for 50Hz ±2%or60Hz±2%.For60Hzrejection,FO (Pin 8) should be connected to GND (Pin 4) while for 50Hz rejection the FO pin should be connected to VCC (Pin 1). The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2420 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The exter- nal clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2420 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 ±4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 5. |
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