LTC2420CS8 datasheet(12/36 Pages) LINER

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LTC2420

APPLICATIO S I FOR ATIO

fault current, a resistor of up to 25k may be added in series

with the VIN pin without affecting the performance of the

device. In the physical layout, it is important to maintain

the parasitic capacitance of the connection between this

series resistance and the VIN pin as low as possible;

therefore, the resistor should be located as close as

practical to the VIN pin. The effect of the series resistance

on the converter accuracy can be evaluated from the

curves presented in the Analog Input/Reference Current

section. In addition, a series resistor will introduce a

temperature dependent offset error due to the input leak-

age current. A 1nA input leakage current will develop a

1ppm offset error on a 5k resistor if VREF = 5V. This error

has a very strong temperature dependency.

Output Data Format

The LTC2420 serial output data stream is 24 bits long. The

first 4 bits represent status information indicating the

sign, input range and conversion state. The next 20 bits are

the conversion result, MSB first.

Bit 23 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 21 (third output bit) is the conversion result sign indi-

cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this

bit is LOW. The sign bit changes state during the zero code.

Bit 20 (fourth output bit) is the extended input range (EXR)

indicator. If the input is within the normal input range

≤ VIN ≤ VREF, this bit is LOW. If the input is outside the

normal input range, VIN > VREF or VIN < 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2420 Status Bits

Bit 23

Bit 22

Bit 21

Bit 20

Input Range

EOC

DMY

SIG

EXR

VIN > VREF

011

0 < VIN ≤ VREF

010

VIN = 0

+/0–

1/0

VIN < 0

001

Bit 19 (fifth output bit) is the most significant bit (MSB).

Bits 19-0 are the 20-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 4. Whenever CS is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 23 (EOC) can be captured on the first rising

edge of SCK. Bit 22 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 23rd SCK and may be latched on

Figure 4. Output Data Timing

MSB

EXT

SIG

“0”

BIT 0

BIT 19

BIT 4

LSB20

BIT 20

BIT 21

BIT 22

SDO

SCK

EOC

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

2420 F04

Hi-Z

LTC2420CS8 Datasheet(PDF) 12 Page - Linear Technology

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