RMLD232UAW datasheet(31/50 Pages) EMLSI

31 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, Temp = -25 to 85 )

NOTE :

1. DPD (Deep Power Down) function is an optional feature, and it will be enabled upon request.

Please contact Ramsway for more information.

2. IDD specifications are tested after the device is properly intialized.

3. Input slew rate is 1V/ .

4. Definitions for IDD:

LOW is defined as VIN

0.1*VDDQ;

HIGH is defined as VIN

0.9*VDDQ;

Parameter

Symbol

Test Condition

DDR

266

DDR

222

Unit

Operating Current

(One Bank Active/Precharge

current)

IDD0

tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; CS is HIGH between valid

commands; address inputs are switching every two clock cycles;

Data bus inputs are stable

Operating Current

(One Bank Active-Read-Pre-

charge current; Burst=4)

IDD1

tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; IOUT = 0 ;

Address and control inputs changing once per clock cycle

100

Precharge Standby

Current in power-down

mode

IDD2P

All banks idle, CKE is LOW; CS is HIGH, tCK=tCKmin;

Address and control inputs are switching every two clock cycles;

Data bus inputs are stable

0.5

IDD2PS

All banks idle, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH;

address and control inputs are switching every two clock cycles;

Data bus inputs are stable

0.5

Precharge Standby

Current in non power-down

mode

IDD2N

All banks idle, CKE is HIGH; CS is HIGH, tCK=tCKmin; Address and

control inputs are switching every two clock cycles;

Data bus inputs are stable

IDD2NS

All banks idle, CKE is HIGH; CS is HIGH, CK=LOW, CK=HIGH;

Address and control inputs are switching every two clock cycles;

Data bus inputs are stable

Active Standby Current

in power-down mode

IDD3P

One bank active, CKE is LOW; CS is HIGH, tCK=tCKmin;

Address and control inputs switching every two clock cycles;

Data bus inputs are stable

IDD3PS

One bank active, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH;

Address and control inputs are switching every two clock cycles;

Data bus inputs are stable

Active Standby Current

in non power-down mode

(One Bank Active)

IDD3N

One bank active, CKE is HIGH; CS is HIGH, tCK=tCKmin;

Address and control inputs switching every two clock cycles;

Data bus inputs are stable

IDD3NS

One bank active, CKE is HiGH; CS is HIGH, CK=LOW, CK=HIGH;

Address and control inputs are switching every two clock cycles;

Data bus inputs are stable

Operating Current

(Burst Mode)

IDD4R

One bank active; BL=4; CL=3; tCK=tCKmin; Continuous read bursts;

IOUT = 0 ; Address inputs are switching;

50% data change each burst tranfer

120

115

IDD4W

One bank active; BL=4; tCK=tCKmin; Continuous write bursts;

Address inputs are switching; 50% Data change each burst transfer

100

Refresh Current

IDD5

tRC=tRFCmin; tCK=tCKmin; burst refresh; CKE is HIGH;

Address and control inputs are switching; Data businputs are stable

100

Self Refresh Current

IDD6

CKE is LOW; tCK= tCKmin ;

Extended Mode Register set to all 0’s; address

and control inputs are stable; Data bus inputs

are stable

TCSR Range

Max

4 Banks

220

250

2 Banks

170

190

1 Bank

135

150

Deep Power Down Current

IDD8*1

Address and control inputs are stable; Data bus inputs are stable

RMLD232UAW Datasheet(PDF) 31 Page - Emerging Memory & Logic Solutions Inc

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