RMLD232UAW datasheet(13/50 Pages) EMLSI

13 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Burst Write Operation

The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The

address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The

first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after

tDQSS from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each

subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any

additional data supplied to the DQ pins will be ignored.

1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge.

The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.

If a previous write was in progress, DQS could be High at this time, depending on tDQSS.

Command

NOP

tWPRES*1

tDQSSmax

DQS

DQs

Figure.6 Burst write operation timing

< Burst Length=4 >

WRITEA

WRITEB

Din 0 Din 1 Din 2 Din 3 Din 0

Din 2

Din 1

Din 3

RMLD232UAW Datasheet(PDF) 13 Page - Emerging Memory & Logic Solutions Inc