AS3412 datasheet(72/85 Pages) AMSOSRAM

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ams Datasheet

Page 71

[v1-00] 2016-Apr-06

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AS3412 − Register Description

Figure 88:

CONFIG_2 Register Description

Name

Address

Default Value

CONFIG_2

0x3F

0x00

This register controls the register access to all OTP registers. In order to get access to these registers it is

necessary to set EVAL_REG_ON bit to ‘1’.

Bit

Bit Name

Default

Access

Bit Description

5TM34

R/W

This Register defines the register bank selection for

TM34 you can select either between Register bank

0x10-0x17 or 0x30h-0x34.

0: Test mode Registers 14h-17h and 10h-13h

disabled test mode Registers 30h-33h and

34h-37h enabled

1: Test mode Registers 14h-17h and 10h-13h enabled

test mode Registers 30h-33h and 34h-37h disabled

4BURNSW

R/W

This register controls the internal buffer switch from

line input to VNEG for VNEG buffering during OTP

programming.

0: BURN switch disabled

1: BURN switch enabled

3TM_REG34-35

R/W

0: Register 34h-35h disabled

1: Register 34h-35h enabled

2TM_REG30-33

R/W

0: Register 30h-33h disabled

1: Register 30h-33h enabled

1:0

OTP_MODE<1:0>

R/W

This register controls the OTP access.

00: READ

01: LOAD

10: WRITE

11: BURN

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