AS3412 datasheet(56/85 Pages) AMSOSRAM

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ams Datasheet

Page 55

[v1-00] 2016-Apr-06

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AS3412 − Register Description

Detailed Register Description

System Registers

Figure 70:

SYSTEM Register Description

Name

Address

Default Value

SYSTEM

0x20

81h

This register contains control bits for monitor mode, OTP register and power up/down functions.

Bit

Bit Name

Default

Access

Bit Description

7:4

DESIGN_VERSION

1111

Design version number to identify the design version

of the AS3412.

1111: for chip version 1v0

3EVAL_REG_ON

R/W

This register controls read and write access to the OTP

0: Normal operation

1: Enables writing to register 0x3D, 0x3E and 0x3F to

configure the OTP and set the access mode.

0PWR_HOLD

R/W

This bit allows an MCU using the I²C interface a power

down of the AS3412. A start condition on the I²C

interface will wake up the device again. This function

works only if the I2C_MODE bit is set before you write

this register.

0: Power up hold is cleared and chip powers down

1: It is automatically set to on after power on

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