AS3412 datasheet(45/85 Pages) AMSOSRAM

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[v1-00] 2016-Apr-06

AS3412 − Detailed Description

Figure 57:

Timing Diagram VNEG Buffering

VNEG Buffer Timing: This timing diagram shows how to buffer the VNEG supply during the OTP programming

process.

To guarantee a successful trimming process it is important to

follow the predefined trimming sequence shown in Figure 57.

As a first step it is important to do a register dump of all OTP

registers. This register backup in your system memory is a

backup of all register settings and is necessary for verification

after the trim process to make sure that all bits are trimmed

correctly. Once the register dump has been done it is important

to check registers 0x30 and 0x31. These registers typically

indicate if the device is already trimmed or not. If both registers

have the value 0x80 you can enter the trim mode and start the

trimming process. Once trimming is done, the most important

step is comparing the values trimmed to the device with the

original register dump performed just before we started the

actual trimming process. If the verification was successful we

know that all bits have been trimmed correctly. What is

important to mention is that the AS3412 has a couple of test

bits inside which are by default set to ‘1’. We do not recommend

overwriting these bits. Furthermore, it is important to know that

it is not possible to change bits once they are trimmed. It is not

possible to change a bit from ‘1’ back to zero. If an additional

trimming is done it is only possible to change bits from ‘0’ to

‘1’. It is important that all necessary bits are trimmed exactly like

in the block diagram shown in Figure 58.

VBAT

MODE/CSCL

VOL/CSDA

VNEG OK

VNEG BUFFER ON

>10ms

~1ms

Start Trim-Process

AS3412 Datasheet(PDF) 45 Page - ams-OSRAM AG