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TBD Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

No. de pieza TBD
Descripción Electrónicos  Quad Core Digital Signal Processor
PDF  80 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
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TBD Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
46
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
800
800
ps
±100 ppm
Table 38. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
400
400
ps
±100 ppm
Table 39. Receiver AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
22
ns
Skew at the receiver input between lanes of a
multilane link
Table 37. Receiver AC Timing Specifications—1.25 GBaud (continued)
Characteristic
Symbol
Range
Unit
Notes
Min
Max



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