LIS2DUX12TR datasheet(42/102 Pages) STMICROELECTRONICS

42 / 102 page

8.9

FIFO_CTRL (15h)

R/W

CFG_CHG_EN

FIFO_

DEPTH

0(1)

STOP_ON

_FTH

FIFO_MODE2

FIFO_MODE1

FIFO_MODE0

1. This bit must be set to 0 for the correct operation of the device.

Table 38. FIFO_CTRL register description

CFG_CHG_EN

Enables batching in FIFO of the device configuration and timestamp value when the ODR (output data

rate) or the BDR (batch data rate) changes. Default value: 0

(0: disabled; 1: enabled)

FIFO_DEPTH

If 1, enables 2x depth mode for FIFO buffer.

STOP_ON_FTH

Sensing chain FIFO stop values memorization at threshold level.

(0: FIFO depth is not limited (default);

1: FIFO depth is limited to threshold level)

FIFO_MODE[2:0](1) Different FIFO modes are enabled as shown in Table 39.

1. User must set the FIFO_EN bit to 1 in the CTRL4 (13h) register before setting the FIFO_MODE[2:0] bits.

Table 39. Selection of FIFO mode

FIFO_MODE2 FIFO_MODE1 FIFO_MODE0

Mode

Bypass mode

FIFO mode: stops collecting data when FIFO is full

Reserved

Continuous-to-FIFO: stream mode until trigger is deasserted, then FIFO

mode

Bypass-to-continuous: bypass mode until trigger is deasserted, then

continuous mode

Reserved

Continuous mode: if the FIFO is full, the new sample overwrites the older

sample.

Bypass-to-FIFO: bypass mode until trigger is deasserted, then FIFO mode

LIS2DUX12

FIFO_CTRL (15h)

DS14071 - Rev 2

page 42/102

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