LIS2DUX12TR datasheet(71/102 Pages) STMICROELECTRONICS

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10.14

FSM_STATUS (13h)

Finite state machine status register (R)

Table 157. FSM_STATUS register

IS_FSM8

IS_FSM7

IS_FSM6

IS_FSM5

IS_FSM4

IS_FSM3

IS_FSM2

IS_FSM1

Table 158. FSM_STATUS register description

IS_FSM8

Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM7

Interrupt status bit for FSM7 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM6

Interrupt status bit for FSM6 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM5

Interrupt status bit for FSM5 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM4

Interrupt status bit for FSM4 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM3

Interrupt status bit for FSM3 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM2

Interrupt status bit for FSM2 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_FSM1

Interrupt status bit for FSM1 interrupt event. (1: interrupt detected; 0: no interrupt)

10.15

MLC_STATUS (15h)

Machine learning core status register (R)

Table 159. MLC_STATUS register

IS_MLC4

IS_MLC3

IS_MLC

IS_MLC1

Table 160. MLC_STATUS register description

IS_MLC4

Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC3

Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC2

Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt)

IS_MLC1

Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt)

LIS2DUX12

FSM_STATUS (13h)

DS14071 - Rev 2

page 71/102

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