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LIS2DUX12TR Datasheet(PDF) 82 Page - STMicroelectronics |
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LIS2DUX12TR Datasheet(HTML) 82 Page - STMicroelectronics |
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82 / 102 page ![]() 10.37 FSM_ODR (39h) Finite state machine output data rate configuration register (R/W) Table 207. FSM_ODR register 0(1) 1(2) FSM_ODR_2 FSM_ODR_1 FSM_ODR_0 0(1) 0(1) 0(1) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 208. FSM_ODR register description FSM_ODR_[2:0] Finite state machine ODR configuration: (000: 12.5 Hz; 001: 25 Hz (default); 010: 50 Hz; 011: 100 Hz; 100: 200 Hz; 101: 400 Hz; 110: 800 Hz) 10.38 MLC_ODR (3Ah) Machine learning core output data rate configuration register (R/W) Table 209. MLC_ODR register 0(1) MLC_ODR_2 MLC_ODR_1 MLC_ODR_0 0(1) 0(1) 0(1) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 210. MLC_ODR register description MLC_ODR_[2:0] Machine learning core ODR configuration: (000: 12.5 Hz; 001: 25 Hz (default); 010: 50 Hz; 011: 100 Hz; 100: 200 Hz) LIS2DUX12 FSM_ODR (39h) DS14071 - Rev 2 page 82/102 |
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