4

P/N: PM1141

REV. 1.1, MAY. 04, 2005

MX23L12854

SPI MODES

These devices can be driven by a microcontroller with its

SPI peripheral running in either of the two following modes:

- CPOL=0, CPHA=0

- CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising

edge of Serial Clock (C), and output data is available from

the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure

2, is the clock polarity when the bus master is in Stand-by

mode and not transferring data:

- C remains at 0 for (CPOL=0, CPHA=0)

- C remains at 1 for (CPOL=1, CPHA=1)

Figure 1. Bus Master and Memory Devices on the SPI Bus

Note: 1. Hold (HOLD#) signals should be driven, High or Low as appropriate.

Figure 2. SPI Modes Supported

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

S#

CS3

CS2

CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD#

S#

HOLD#

S#

HOLD#

C

MSB

CPHA

D

0

1

CPOL

0

1

Q

C

MSB