8

P/N: PM1141

REV. 1.1, MAY. 04, 2005

MX23L12854

Figure 5. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out

Sequence

23

2

1

3456789 10

28 29 30 31

22 21

3210

High Impedance

Instruction

24 BIT ADDRESS

0

32 33 34

36 37 38 39 40 41 42 43 44 45 46

765432

0

1

DATA OUT 1

Dummy Byte

MSB

7

6543210

DATA OUT 2

MSB

MSB

7

47

765432

0

1

35

C

D

S#

Q

C

D

S#

Q

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S#)

Low. The instruction code for the Read Data Bytes at

Higher Speed (FAST_READ) instruction is followed by a 3-

byte address (A23-A0) and a dummy byte, each bit being

latched-in during the rising edge of Serial Clock (C). Then

the memory contents, at that address, is shifted out on

Serial Data Output (Q), each bit being shifted out, at a

maximum frequency fC, during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Figure 5. The first

byte addressed can be at any location. The address is

automatically incremented to the next higher address after

each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher

Speed (FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to 000000h,

allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ)

instruction is terminated by driving Chip Select (S#) High.

Chip Select (S#) can be driven High at any time during data

output.