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WM8581 Datasheet(PDF) 27 Page - Wolfson Microelectronics plc |
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WM8581 Datasheet(HTML) 27 Page - Wolfson Microelectronics plc |
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27 / 94 page  Product Preview WM8581 w PP Rev 1.0 March 2006 27 Figure 21 DSP Mode B Timing Diagram - SAIF Receiver Input Data The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data. Figure 22 DSP Mode B Timing Diagram – PAIF/SAIF Transmitter Data AUDIO INTERFACE CONTROL The register bits controlling the audio interfaces are summarized below. Dynamically changing the audio data format may cause erroneous operation, and is not recommended. Interface timing is such that the input data and LRCLK are sampled on the rising edge of the interface BCLK. Output data changes on the falling edge of the interface BCLK. By setting the appropriate bit clock polarity control register bits, e.g. PAIFRXBCP, the polarity of BCLK may be reversed, allowing input data and LRCLK to be sampled on the falling edge of BCLK. Setting the bit clock polarity register for a transmit interface results in output data changing on the rising edge of BCLK. Similarly, the polarity of left/right clocks can be reversed by setting the appropriate left right polarity bits, e.g. PAIFRXLRP. |
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