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DS31256 Datasheet(PDF) 39 Page - Maxim Integrated Products |
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DS31256 Datasheet(HTML) 39 Page - Maxim Integrated Products |
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39 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 39 of 183 Bit 15/Status Bit for Local Bus Interrupt (LBINT) 0 = interrupt masked 1 = interrupt unmasked Register Name: SV54 Register Description: Status Register for the Receive V.54 Detector Register Address: 0030h Bit # 7 6 5 4 3 2 1 0 Name SLBP7 SLBP6 SLBP5 SLBP4 SLBP3 SLBP2 SLBP1 SLBP0 Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name SLBP15 SLBP14 SLBP13 SLBP12 SLBP11 SLBP10 SLBP9 SLBP8 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Status Bits for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15). These status bits are set to 1 when the V.54 loopback detector within the port has either timed out in its search for the loop-up pattern or it has detected and validated the loop-up or loop-down pattern. There is one status bit per port. The host must read the VTO and VLB status bits in RP[n]CR register of the corresponding port to determine the exact status of the V.54 detector. If the V.54 detector has timed out in its search for the loop-up code (VTO = 1), then SLBP is continuously set until the host resets the V.54 detector by toggling the VRST bit in RP[n]CR. If enabled through the SLBP[n] bit in the interrupt mask for SV54 (ISV54), the setting of these bits causes a hardware interrupt at the PCI bus through the PINTA signal pin and also at the LINT if the local bus is in configuration mode. See Section 6 for specific details about the operation of the V.54 loopback detector. Register Name: ISV54 Register Description: Interrupt Mask Register for SV54 Register Address: 0034h Bit # 7 6 5 4 3 2 1 0 Name SLBP7 SLBP6 SLBP5 SLBP4 SLBP3 SLBP2 SLBP1 SLBP0 Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name SLBP15 SLBP14 SLBP13 SLBP12 SLBP11 SLBP10 SLBP9 SLBP8 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/Status Bit for Change of State in Receive V.54 Loopback Detector (SLBP0 to SLBP15) 0 = interrupt masked 1 = interrupt unmasked |
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