DS31256_V01 datasheet(87/183 Pages) MAXIM

No. de pieza	DS31256

Descripción Electrónicos	256-Channel, High-Throughput HDLC Controller

PDF	183 Pages

Scroll/Zoom	100%

Fabricante Electrónico	MAXIM [Maxim Integrated Products]

Página de inicio	https://www.maximintegrated.com/en.html

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DS31256 256-Channel, High-Throughput HDLC Controller

87 of 183

Host Actions

The host typically handles the receive DMA as follows:

1) The host is always trying to make free data buffer space available and therefore tries to fill the free-

queue descriptor.

2) The host either polls, or is interrupted, when some incoming packet data is ready for processing.

3) The host then reads the done-queue descriptor circular queue to find out which channel has data

available, what the status is, and where the receive packet descriptor is located.

4) The host then reads the receive packet descriptor and begins processing the data.

5) The host then reads the next descriptor pointer in the link-listed chain and continues this process

until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been

reached.

6) The host then checks the done-queue descriptor circular queue to see if any more data buffers are

ready for processing.

DS31256 Datasheet(PDF) 87 Page - Maxim Integrated Products