DS31256_V01 datasheet(57/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Table 6-B. Receive V.54 Search Routine

STEP

DIRECTION

FUNCTION

Set up the channel search

By configuring the RV54 bit in the R[n]CFG[j] register, the host

determines in which DS0 channels the V.54 search is to take place. If

this search sequence does not detect the V.54 pattern, the host can pick

some new DS0 channels and try again.

Toggle VRST

Once the DS0 channels have been set, the host toggles the VRST bit in

the RP[n]CR register and begins monitoring the SLBP status bit.

Wait for SLBP

The SLBP status bit reports any change of state in the V.54 search

process. It can also generate a hardware interrupt (Section 5). When

SLBP is set, the host knows that something significant has occurred and

that it should read the VLB and VTO real-time status bits in the

RP[n]CR register.

Read VTO and VLB

If VTO = 1, the V.54 pattern did not appear in this set of channels and

the host can reconfigure the search in other DS0 channels and move

back to Step #1.

If VLB = 1, the V.54 loop-up pattern has been detected and the channel

should be placed into loopback. A loopback can be invoked by the host

by configuring the CNLB bit in the T[n]CFG[j] register for each DS0

channel that needs to be placed into loopback. Move back to Step #3.

If VLB = 0, if the DS0 channels are already in loopback, the host

monitors VLB to know when the loop-down pattern has been detected

and when to take the channels out of loopback. The DS0 channels are

taken out of loopback by again configuring the CNLB bits. Move on to

Step #1.

DS31256 Datasheet(PDF) 57 Page - Maxim Integrated Products