K32L2AX datasheet(79/96 Pages) NXP

79 / 96 page

8.8.4 LPSPI switching specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable.

The following tables provide timing characteristics for classic SPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,

as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI

pins.

NOTE

• Slew rate disabled pads are those pins with

PORTx_PCRn[SRE] bit cleared. Slew rate enabled pads

are those pins with PORTx_PCRn[SRE] bit set.

• To achieve high bit rate, it is recommended to use fast

pins (PTE20, PTE21, PTE22, PTE23, PTD4, PTD5,

PTD6, and PTD7) and/or high drive pins (PTC3, PTC4,

PTD4, PTD5, PTD6, and PTD7).

Table 48. LPSPI master mode timing on slew rate disabled pads

Num.

Symbol

Description

Min.

Max.

Unit

Note

fop

Frequency of operation

fperiph/2048

fperiph/2

tSPSCK

SPSCK period

2 x tperiph

2048 x

tperiph

tLead

Enable lead time

1/2

—

tSPSCK

—

tLag

Enable lag time

1/2

—

tSPSCK

—

tWSPSCK Clock (SPSCK) high or low time

tperiph - 30

1024 x

tperiph

—

tSU

Data setup time (inputs)

—

tHI

Data hold time (inputs)

—

Data valid (after SPSCK edge)

—

tHO

Data hold time (outputs)

—

tRI

Rise time input

—

tperiph - 25

—

tFI

Fall time input

tRO

Rise time output

—

tFO

Fall time output

1. fperiph is the LPSPI peripheral functional clock.

2. tperiph = 1/fperiph

Peripheral operating requirements and behaviors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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