K32L2AX datasheet(46/96 Pages) NXP

46 / 96 page

Table 17. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

105

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

ILPI2C

LPI2C peripheral adder measured by

placing the device in VLPS mode with

selected clock source, LPI2C is

configured as master, and bit rate is

400 Kbps. Includes selected clock

source power consumption.

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

69.7

582.9

66.7

597.9

66.9

610.8

67.6

623.8

68.2

637.0

68.2

660.2

µA

IBG

Bandgap adder when BGEN bit is set

and device is placed in VLPS mode.

• Bandgap buffer disabled

• Bandgap buffer enabled

96.8

137.5

95.4

129.6

96.4

133.0

98.2

135.5

98.2

136.9

98.5

139.6

µA

IADC

ADC peripheral adder combining the

measured values at VDD and VDDA by

placing the device in STOP mode. ADC

is configured for low power mode using

the ADC asynchronous clock (ADACK)

and continuous conversions.

372.9

380.5

384.0

388.3

392.2

394.6

µA

IWDOG

WDOG peripheral adder measured by

placing the device in STOP mode,

WDOG is configured to time out at 1

second. Includes selected clock source

power consumption.

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

• LPO (internal 1 kHz Lower Power

Oscillator)

68.8

11.2

56.0

68.5

10.1

57.1

69.2

10.1

58.6

69.9

10.2

58.5

71.7

10.5

58.6

72.6

10.7

60.0

µA

ISIRC_8MHz

SIRC adder when SIRC is configured to

8 MHz. Measured by entering VLPS

mode with 8 MHz IRC enabled, and

SIRCDIV1, SIRCDIV2, SIRCDIV3 =000.

67.2

63.0

63.3

63.2

63.3

63.6

µA

ISIRC_2MHz

SIRC adder when SIRC is configured to

2 MHz. Measured by entering STOP or

VLPS mode with 2 MHz IRC enabled,

and SIRCDIV1, SIRCDIV2, SIRCDIV3

=000.

22.3

21.2

21.4

21.5

21.7

21.4

µA

General

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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