UCD7100 datasheet(10/22 Pages) TI

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Thermal Information

P + 10 nF

122

300 kHz + 0.432 W

(3)

I +

0.432 W

12 V

+ 0.036 A

(4)

Circuit Layout Recommendations

P + C

f + QG

(5)

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

With V

DD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the

power loss can be calculated as:

The useful range of a driver is greatly affected by the

drive power requirements of the load and the thermal

characteristics of the device package. In order for a

With a 12-V supply, this would equate to a current of:

power driver to be useful over a particular tempera-

ture range the package must allow for the efficient

removal of the heat produced while keeping the

junction temperature within rated limits. The UCD7K

The actual current measured from the supply was

family of drivers is available in PowerPAD™ TSSOP

0.037 A, and is very close to the predicted value. But,

and QFN/DFN packages to cover a range of appli-

the IDD current that is due to the device internal

cation requirements. Both have the exposed pads to

consumption should be considered. With no load the

relieve thermal dissipation from the semiconductor

device current drawn is 0.0027 A. Under this con-

junction.

dition the output rise and fall times are faster than

with a load. This could lead to an almost insignificant,

As illustrated in Reference [2], the PowerPAD™

yet measurable current due to cross-conduction in the

packages offer a leadframe die pad that is exposed at

output stages of the driver. However, these small

the base of the package. This pad is soldered to the

current differences are buried in the high frequency

copper on the PC board (PCB) directly underneath

switching spikes, and are beyond the measurement

the device package, reducing the

down to

capabilities of a basic lab setup. The measured

4.7

°C/W. The PC board must be designed with

current with 10-nF load is close to the value ex-

thermal lands and thermal vias to complete the heat

pected.

removal subsystem, as summarized in Reference [3].

The switching load presented by a power MOSFET

Note that the PowerPAD™ is not directly connected

can be converted to an equivalent capacitance by

to any leads of the package. However, it is electrically

examining the gate charge required to switch the

and thermally connected to the substrate which is the

device. This gate charge includes the effects of the

ground of the device.

input capacitance plus the added charge needed to

swing the drain of the device between the ON and

OFF states. Most manufacturers provide specifi-

In a power driver operating at high frequency, it is a

cations that provide the typical and maximum gate

significant challenge to get clean waveforms without

charge, in nC, to switch the device under specified

much overshoot/undershoot and ringing. The low

conditions. Using the gate charge QG, one can

output

impedance

these

drivers

produces

determine the power that must be dissipated when

waveforms with high di/dt. This tends to induce

charging a capacitor. This is done by using the

ringing in the parasitic inductances. Utmost care must

equivalence QG = CEFF x V to provide the following

be used in the circuit layout. It is advantageous to

equation for power:

connect the driver IC as close as possible to the

leads. The driver device layout has the analog ground

on the opposite side of the output, so the ground

This equation allows a power designer to calculate

should be connected to the bypass capacitors and

the bias power required to drive a specific MOSFET

the load with copper trace as wide as possible. These

gate at a specific bias voltage.

connections should also be made with a small en-

closed loop area to minimize the inductance.

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