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Handshaking

Drive Current and Power Requirements

Driver Output

E +

CV2

(1)

P +

CV2

(2)

Source/Sink Capabilities During Miller Plateau

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

flag is latched high and the digital controller must poll

drain voltage is swinging between the voltage levels

the UCD7K device, by sending it a narrow IN pulse. If

dictated by the power topology, requiring the charg-

the fault condition is not present the IN pulse resets

ing/discharging of the drain-gate capacitance with

the CLF signal to low indicating that the UCD7K

current supplied or removed by the driver device. See

device is ready to process power pulses.

Reference [1]

The UCD7K family of devices have a built-in hand-

The UCD7K family of drivers can deliver high current

shaking feature to facilitate efficient start-up of the

into a MOSFET gate for a period of several hundred

digitally controlled power supply. At start-up the CLF

nanoseconds. High peak current is required to turn

flag is held high until all the internal and external

the device ON quickly. Then, to turn the device OFF,

supply voltages of the UCD7K device are within their

the driver is required to sink a similar amount of

operating range. Once the supply voltages are within

current to ground. This repeats at the operating

acceptable limits, the CLF goes low and the device

frequency of the power device. A MOSFET is used in

will process input drive signals. The micro-controller

this discussion because it is the most common type

should monitor the CLF flag at start-up and wait for

of switching device used in high frequency power

the CLF flag to go LOW before sending power pulses

conversion equipment.

to the UCD7K device.

Reference [1] discusses the current required to drive

power

MOSFET

and

other

capacitive-input

switching devices.

The high-current output stage of the UCD7K device

When a driver device is tested with a discrete,

family is capable of supplying

±4-A peak current

capacitive load it is a fairly simple matter to calculate

pulses and swings to both VDD and GND. The driver

the power that is required from the bias supply. The

outputs follows the state of the IN pin provided that

energy that must be transferred from the bias supply

the VDD and 3V3 voltages are above their respective

to charge the capacitor is given by:

under-voltage lockout threshold.

The

drive

output

utilizes

Texas

Instruments’

TrueDrive™ architecture, which delivers rated current

where C is the load capacitor and V is the bias

into the gate of a MOSFET when it is most needed

voltage feeding the driver.

during the Miller plateau region of the switching

transition providing efficiency gains.

There is an equal amount of energy transferred to

ground when the capacitor is discharged. This leads

TrueDrive™ consists of pullup/ pulldown circuits

to a power loss given by the following:

using bipolar and MOSFET transistors in parallel. The

peak output current rating is the combined current

from the bipolar and MOSFET transistors. The output

resistance is the RDS(on) of the MOSFET transistor

where f is the switching frequency.

when the voltage on the driver output is less than the

saturation voltage of the bipolar transistor. This hybrid

This power is dissipated in the resistive elements of

output stage also allows efficient current sourcing at

the circuit. Thus, with no external resistor between

low supply voltages.

the driver and gate, this power is dissipated inside the

driver. Half of the total power is dissipated when the

Each output stage also provides a very low im-

capacitor is charged, and the other half is dissipated

pedance to overshoot and undershoot due to the

when the capacitor is discharged. An actual example

body diode of the external MOSFET. This means that

using the conditions of the previous gate drive

in many cases, external-schottky-clamp diodes are

waveform should help clarify this.

not required.

Large power MOSFETs present a large load to the

control circuitry. Proper drive is required for efficient,

reliable operation. The UCD7K drivers have been

optimized to provide maximum drive to a power

MOSFET during the Miller plateau region of the

switching transition. This interval occurs while the

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