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UCD7100 Datasheet(PDF) 5 Page - Texas Instruments |
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UCD7100 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 22 page ![]() www.ti.com VIT− 10% 90% INPUT OUTPUT VIT+ tD1 tF tF tD2 UCD7100 SLUS651A – MARCH 2005 – REVISED MAY 2005 ELECTRICAL CHARACTERISTICS (continued) V DD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = -40°C to 105°C, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS Source current (1) VDD = 12 V, IN = high, OUT = 5 V 4 Sink current (1) VDD = 12 V, IN = low, OUT = 5 V 4 A Source current(1) VDD = 4.75 V, IN = high, OUT = 0 2 Sink current (1) VDD = 4.75 V, IN = low, OUT = 4.75 V 3 Rise time, tR(1) CLOAD = 2.2 nF, VDD = 12 V 10 20 ns Fall time, tF(1) CLOAD = 2.2 nF, VDD = 12 V 10 15 Output with VDD < UVLO VDD = 1.0 V, ISINK = 10 mA 0.8 1.2 V Propagation delay from IN to OUTx, CLOAD = 2.2 nF, VDD = 12 V, CLK rising 20 35 ns tD1 (1) Ensured by design. Not 100% tested in production. NOTE: The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. 5 |
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