UCD7100 datasheet(4/22 Pages) TI

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ELECTRICAL CHARACTERISTICS

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

DD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = -40°C to 105°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY SECTION

Supply current, OFF

VDD = 4.2 V

200

400

µA

Supply current

Outputs not switching IN = LOW

1.5

2.5

LOW VOLTAGE UNDER-VOLTAGE LOCKOUT

VDD UVLO ON

4.25

4.5

4.75

VDD UVLO OFF

4.05

4.25

4.45

VDD UVLO hysteresis

150

250

350

REFERENCE / EXTERNAL BIAS SUPPLY

3V3 initial set point

TA = 25°C

3.267

3.3

3.333

3V3 over temperature

3.234

3.3

3.366

3V3 load regulation

ILOAD = 1 mA to 10 mA, VDD = 5 V

6.6

3V3 line regulation

VDD = 4.75 V to 12 V, ILOAD = 10 mA

6.6

Short circuit current

VDD = 4.75 to 12 V

3V3 OK threshold, ON

3.3 V rising

2.9

3.0

3.1

3V3 OK threshold, OFF

3.3 V falling

2.7

2.8

2.9

INPUT SIGNAL

HIGH, positive-going input threshold

1.65

2.08

voltage (VIT+)

LOW negative-going input threshold

1.16

1.5

voltage (VIT-)

Input voltage hysteresis, (VIT+ -

0.6

0.8

VIT-)

Frequency

MHz

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold

ILIM = OPEN

0.466

0.50

0.536

ILIM maximum current limit threshold

ILIM = 3.3 V

0.975

1.025

1.075

ILIM current limit threshold

ILIM = 0.75 V

0.700

0.725

0.750

ILIM minimum current limit threshold

ILIM = 0.25 V

0.21

0.23

0.25

CLF output high level

CS > ILIM , ILOAD = -7 mA

2.64

CLF output low level

≤ I

LIM, ILOAD = 7 mA

0.66

Propagation delay from IN to CLF

IN rising to CLF falling after a current limit event

CURRENT SENSE COMPARATOR

Bias voltage

Includes CS comp offset

Input bias current

–1

Propagation delay from CS to OUTx

ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV

Propagation delay from CS to CLF

ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance

IN = low, resistance from CS to AGND

Ω

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