5222-DS00-R datasheet(28/76 Pages) BOARDCOM

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BCM5222

Preliminary Data Sheet

7/20/04

Broadcom Corporation

Page 16

Document 5222-DS02-405-R

Section 5: Register Summary

MEDIA INDEPENDENT INTERFACE (MII) MANAGEMENT INTERFACE:

The BCM5222 fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management

interface registers are serially written to and read from using the MDIO and MDC pins. A single clock waveform must be

provided to the BCM5222 at a rate of 0–25MHz through the MDC pin. The serial data is communicated on the MDIO pin.

Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched on the rising edge of the MDC

clock.

See Table 6 for the fields in every MII instruction’s read or write packet frame.

PREAMBLE (PRE)

32 consecutive 1 bits must be sent through the MDIO pin to the BCM5222 to signal the beginning of an MII instruction. Fewer

than 32 1 bits causes the remainder of the instruction to be ignored, unless the Preamble Suppression mode is enabled

(register 01, bit 6).

START OF FRAME (ST)

A 01 pattern indicates that the start of the instruction follows.

OPERATION CODE (OP)

A read instruction is indicated by 10, while a write instruction is indicated by 01.

PHY ADDRESS (PHYAD)

A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single MDIO bus to access

multiple transceivers. The BCM5222 supports the full 32-PHY address space.

A 5-bit register address follows, with the MSB transmitted first. The register map of the BCM5222, containing register

addresses and bit definitions, are provided on the following pages.

Table 6: MII Management Frame Format

Operation

PRE

PHYAD

Regad

Data

idle

Direction

READ

1 ... 1

AAAAA

RRRRR

Z... Z

D ... D

Driven to BCM5222

Driven by BCM5222

WRITE

1 ... 1

AAAAA

RRRRR

D ... D

Driven to BCM5222

5222-DS00-R Datasheet(PDF) 28 Page - Broadcom Corporation.

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