SEPTEMBER 2010

DSC-5304/07

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Pin Description Summary

Description

The AS8C803601/801801 are3.3V high-speed 9,437,184 bit

(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT

TM

, or Zero Bus Turnaround.

Features

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256K x 36, 512K x 18 memory configurations

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Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

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Internally synchronized output buffer enable eliminates the

need to control OE

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Single R/W (READ/WRITE) control pin

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Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

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4-word burst capability (interleaved or linear)

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Three chip enables for simple depth expansion

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3.3V power supply (±5%)

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Power down controlled by ZZ input

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Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP).

Address Inputs

Input

Synchronous

Chip Enables

Input

Synchronous

OE

Output Enable

Input

Asynchronous

R/W

Read/Write S ignal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/LD

Advance burst address / Load new address

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

Static

ZZ

Sleep Mode

Input

Asynchronous

Data Input / Output

I/O

Synchronous

Core P ower, I/O Power

Supply

Static

Ground

Supply

Static

5304 tbl 01

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

ZBT™ Feature

3.3V I/O, Burst Counter

Pipelined Outputs

AS8C803601

AS8C801801

Address and control signals are applied to the SRAM during one clock

cycle, andtwo cycles later theassociated data cycle occurs, be it read or write.

TheAS8C803601/801801 contain data I/O, address and control signal

registers. Output enable is the only asynchronoussignal and can be

used to disable the outputsat any given time.

A Clock Enable(CEN) pin allows operation of the toAS8C803601/ 801801

be suspended aslong as necessary. All synchronousinputs are ignored when

(CEN)is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2,CE2) that allow the user

to deselect the device when desired. If anyone of these threeare not asserted

when ADV/LD is low, no new memoryoperation can be initiated. However,

any pending data transfers (reads or writes) will be completed. The data bus

will tri-state two cycles after chip is deselected or a write is initiated.

TheAS8C803601/801801 have an on-chip burst counter. In the burst

mode,the AS8C803601/801801 can provide fourcycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The AS8C803601/801801 SRAM utilize IDT's latest high-performance

CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100-

pin thin plasticquad flatpack (TQFP) .