AS8C803601 datasheet(10/21 Pages) ALSC

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AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with

ZBT™

™

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial Temperature Range

Burst Write Operation(1)

Burst Read Operation(1)

Write Operation(1)

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

I/O

Comments

nA0

Address and Control meet setup

n+1

Clock Setup Valid, Advance Counter

n+2

Address A0 Read Out, Inc. Count

n+3

Q0+1 Address A0+1 Read Out, Inc . Co unt

n+4

Q0+2 Address A0+2 Read Out, Inc . Co unt

n+5

Q0+3 Address A0+3 Read Out, Load A1

n+6

Address A0 Read Out, Inc. Count

n+7

Address A1 Read Out, Inc. Count

n+8

Q1+1 Address A1+1 Read Out, Load A2

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

I/O

Comments

nA0

Address and Control meet setup

n+1

Clock S etup Valid

n+2

Write to Address A0

CycleAddressR/W

ADV/LD

CE(2)

CEN

I/O

Comments

nA0

Address and Control meet setup

n+1

Clock Setup Valid, Inc. Count

n+2

Address A0 Write, Inc. Count

n+3

D0+1 Address A0+1 Write, Inc. Count

n+4

D0+2

Address A0+2 Write, Inc. Count

n+5

LLL

D0+3

Address A0+3 Write, Load A1

n+6

Address A0 Write, Inc. Count

n+7

Address A1 Write, Inc. Count

n+8

LLL

D1+1 Address A1+1 Write, Load A2

AS8C803601 Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation

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