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AS8C803601 Datasheet(PDF) 13 Page - Alliance Semiconductor Corporation

No. de pieza AS8C803601
Descripción Electrónicos  Three chip enables for simple depth expansion
PDF  21 Pages
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Fabricante Electrónico  ALSC [Alliance Semiconductor Corporation]
Página de inicio  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS8C803601 Datasheet(HTML) 13 Page - Alliance Semiconductor Corporation

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AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™
™
™
™
™
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Industrial Temperature Range)
NOTES:
1. tF = 1/t CYC.
2. Measured as HIGH above 0.6V DDQ and LOW below 0.4V DDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t CHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than
tCHZ
,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
150MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.7
____
7.5
____
10
____
ns
tF(1)
Clock Frequency
____
150
____
133
____
100
MHz
tCH(2)
Clock High Pulse Width
2.0
____
2.2
____
3.2
____
ns
tCL(2)
Clock Low Pulse Width
2.0
____
2.2
____
3.2
____
ns
Output Parameters
tCD
Clock High to Valid Data
____
3.8.
____
4.2
____
5ns
tCDC
Clock High to Data Change
1.5
____
1.5
____
1.5
____
ns
tCLZ(3,4,5)
Clock High to Output A ctive
1.5
____
1.5
____
1.5
____
ns
tCHZ(3,4,5)
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
tOE
Output Enable Access Time
____
3.8
____
4.2
____
5ns
tOLZ(3,4)
Output Enable Low to Data Active
0
____
0
____
0
____
ns
tOHZ(3,4)
Output Enable High to Data High-Z
____
3.8
____
4.2
____
5ns
Set Up Times
tSE
Clock E nable Setup Ti me
1.5
____
1.7
____
2.0
____
ns
tSA
Address Setup Time
1.5
____
1.7
____
2.0
____
ns
tSD
Data In S etup Time
1.5
____
1.7
____
2.0
____
ns
tSW
Read/Write (R/W) Setup Time
1.5
____
1.7
____
2.0
____
ns
tSADV
Advance/Load (ADV/LD)S etup Time
1.5
____
1.7
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
1.7
____
2.0
____
ns
tSB
Byte Write Enable (BWx) Setup Time
1.5
____
1.7
____
2.0
____
ns
Hold Times
tHE
Clock Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
ns
tHW
Read/Write (R/W) Ho ld Time
0.5
____
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/LD)Hold Time
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
0.5
____
0.5
____
ns
5304 tbl 24



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