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AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with

ZBT™

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Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial Temperature Range

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK, ADV/LD low, CEN low, and true chip enables.

ADV/LD

Advance / Load

I

N/A

ADV/LD is a synchronous input that is used to load the internal registers with new address

and control when it is sampled low at the rising edge of clock with the chip selected. When

ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD

is sampled high then the internal burst counter is advanced for any burst that was in

progress. The external addresses are ignored when ADV/LD is s ampled high.

R/W

Read / Write

I

N/A

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a

Read or Write access to the memory array. The data bus activity for the current cycle takes

place two clock cycles later.

CEN

Clock Enable

I

LOW

Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous

inputs, including clock are ignored and outputs remain unchanged. The effect of CEN

sampled high on the device outputs is as if the low to high clock transition did not occur.

For normal operation, CEN must be sampled low at rising edge of clock.

Individual B yte

Write Enables

I

LOW

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.

On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write

a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate

always doing write to the entire 36-bit word.

Chip Enables

I

LOW

the data bus will tri-state two clock cycles after deselect is initiated.

Chip Enable

I

HIGH

CLK

Clock

I

N/A

This is the clock input to theAS8C803601/801801. Except for OE, all timing references for the

device are made with respect to the rising edge of CLK.

Data Inp ut/Output

I/O

N/A

Synchronous data input/output (I/O) p ins. Both the d ata input path and data output p ath are

registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order

I

LOW

Burst order selection input. When LBO is high the Interleaved burst sequence is selected.

When LBO is low the Linear burst sequence is selected. LBO is a static input and it must

not change during device operation.

OE

Output Enable

I

LOW

Asynchronous output enable.OEmust be low to readdata fromtheAS8C803601/801801.When

OE

is high the I/O pins are in a high-impedance state. OE does not need to be actively

controlled for read and write cycles. In normal operation, OE can be tied low.

ZZ

Sleep Mode

I

N/A

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

AS8C803601/801801to its lowest power consumption level.Data retention is guaranteed in

Sleep Mode.

Power Supply

N/A

N/A

3.3V core power supply.

Power Supply

N/A

N/A

3.3V I/O Supply.

Ground

N/A

N/A

Ground.

5304tbl 02