TNETV1644ZDU6 datasheet(220/306 Pages) TI1

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PCLK

(Positive Edge Clocking)

PCLK

(Negative Edge Clocking)

7, 9

HD/VD

CCD[15:0]

8, 10

11, 13

12, 14

C_WE/C_FIELD

PCLK

(Positive Edge Clocking)

CCD[15:0]

C_WE/C_FIELD

PCLK

(Positive Edge Clocking)

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Figure 6-20. VPFE (CCD) Slave Mode Input Data Timing

Table 6-37. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 6-21)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

4.5

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(CWEV-PCLK)

Setup time, C_WE valid before PCLK edge

4.5

th(PCLK-CWEV)

Hold time, C_WE valid after PCLK edge

(1)

The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the

rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

Figure 6-21. VPFE (CCD) Master Mode Input Data Timing

220

Peripheral Information and Electrical Specifications

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