TNETV1644ZDU6 datasheet(219/306 Pages) TI1

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6.10.1.6 VPFE Electrical Data/Timing

PCLK

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-35. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 6-19)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tc(PCLK)

Cycle time, PCLK

10.204 or 13.33(2)

tw(PCLKH)

Pulse duration, PCLK high

0.4P

tw(PCLKL)

Pulse duration, PCLK low

0.4P

tt(PCLK)

Transition time, PCLK

(1)

P = PCLK period in ns.

(2)

When PCLK sources the clock for both the VPFE and VPBE, the minimum cycle time of 13.33 ns (specified in Table 6-42, Timing

Requirements for VPBE CLK Inputs for VPBE) must be met. When PCLK sources the clock for only the VPFE, a minimum cycle time of

10.2 ns may be used.

Figure 6-19. VPFE PCLK Timing

Table 6-36. Timing Requirements for VPFE (CCD) Slave Mode(1) (see Figure 6-20)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

4.5

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(HDV-PCLK)

Setup time, HD valid before PCLK edge

4.5

th(PCLK-HDV)

Hold time, HD valid after PCLK edge

tsu(VDV-PCLK)

Setup time, VD valid before PCLK edge

4.5

th(PCLK-VDV)

Hold time, VD valid after PCLK edge

tsu(C_WEV-PCLK)

Setup time, C_WE valid before PCLK edge

4.5

th(PCLK-C_WEV)

Hold time, C_WE valid after PCLK edge

tsu(C_FIELDV-PCLK)

Setup time, C_FIELD valid before PCLK edge

4.5

th(PCLK-C_FIELDV)

Hold time, C_FIELD valid after PCLK edge

(1)

The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the

rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

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Peripheral Information and Electrical Specifications

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