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TNETV1644ZDU6 Datasheet(PDF) 218 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 218 Page - Texas Instruments |
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218 / 306 page  TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com > region1 > region2 > region3. • Interface to conventional Bayer pattern. Each region can accumulate either 3 or 4 colors. • 32, 64, 128, or 256 bins per color per region. • 32, 64, or 128 bins per color for 2 regions. • 32 or 64 bins per color for 3 or 4 regions. • Automatic clear of histogram RAM after an ARM read. • Saturation of the pixel count if the count exceeds the maximum value (each memory location is 20-bit wide). • Downshift ranging from 0 to 7 bits (maximum bin range 128). • The last bin (highest range of values) will accumulate any value that is higher than the lower bound. The Histogram register memory mapping is shown in Table 6-34. Table 6-34. Histogram Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1000 PID Peripheral Revision and Class Information Register 0x01C7 1004 PCR Peripheral Control Register 0x01C7 1008 HIST_CNT Histogram Control Bits Register 0x01C7 100C WB_GAIN White/Channel Balance Settings Register 0x01C7 1010 R0_HORZ Region 0 Horizontal Information Register 0x01C7 1014 R0_VERT Region 0 Vertical Information Register 0x01C7 1018 R1_HORZ Region 1 Horizontal Information Register 0x01C7 101C R1_VERT Region 1 Vertical Information Register 0x01C7 1020 R2_HORZ Region 2 Horizontal Information Register 0x01C7 1024 R2_VERT Region 2 Vertical Information Register 0x01C7 1028 R3_HORZ Region 3 Horizontal Information Register 0x01C7 102C R3_VERT Region 3 Vertical Information Register 0x01C7 1030 HIST_ADDR Histogram Address for Data to be Read Register 0x01C7 1034 HIST_DATA Histogram Data That is Read From the Memory Register 0x01C7 1038 RADD Read Address From DDR2 Memory Register 0x01C7 103C RADD_OFF Read Address Offset for Each Line in the DDR2 Memory Register 0x01C7 1040 H_V_INFO Horizontal/Vertical Information Register (Horizontal/Vertical Number of Pixels When Data is Read From DDR2 Memory Information Register) Peripheral Information and Electrical Specifications 218 Submit Documentation Feedback |
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