TNETV1644ZDU6 datasheet(213/306 Pages) TI1

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6.10.1.2 Preview Engine

TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-30. CCDC Register Descriptions (continued)

HEX ADDRESS RANGE

DESCRIPTION

0x01C7 0448

VDINT

VD Interrupt Timing

0x01C7 044C

ALAW

A-Law Setting

0x01C7 0450

REC656IF

REC656 Interface

0x01C7 0454

CCDCFG

CCD Configuration

0x01C7 0458

FMTCFG

Data Reformatter/Video Port Configuration

0x01C7 045C

FMT_HORZ

Data Reformatter/Video Input Interface Horizontal Information

0x01C7 0460

FMT_VERT

Data Reformatter/Video Input Interface Vertical Information

0x01C7 0464

FMT_ADDR0

Address Pointer 0 Setup

0x01C7 0468

FMT_ADDR1

Address Pointer 1 Setup

0x01C7 046C

FMT_ADDR2

Address Pointer 2 Setup

0x01C7 0470

FMT_ADDR3

Address Pointer 3 Setup

0x01C7 0474

FMT_ADDR4

Address Pointer 4 Setup

0x01C7 0478

FMT_ADDR5

Address Pointer 5 Setup

0x01C7 047C

FMT_ADDR6

Address Pointer 6 Setup

0x01C7 0480

FMT_ADDR7

Address Pointer 7 Setup

0x01C7 0484

PRGEVEN_0

Program Entries 0-7 for Even Line

0x01C7 0488

RRGEVEN_1

Program Entries 8-15 for Even Line

0x01C7 048C

PRGGODD_0

Program Entries 0-7 for Odd Line

0x01C7 0490

PRGGODD_1

Program Entries 8-15 for Odd Line

0x01C7 0494

VP_OUT

Video Port Output Settings

The preview engine transforms raw unprocessed image/video data from a sensor (CMOS or CCD) into

YCbCr 4:2:2 data. The output of the preview engine is used for both video compression and external

display devices such as a NTSC/PAL analog encoder or a digital LCD. The following features are

supported by the preview engine.

• Accepts conventional Bayer pattern formats.

• Input image/video data from either the CCD/CMOS controller or the DDR2 memory.

• Output width up to 1280 pixels wide.

• Automatic/mandatory cropping of pixels/lines when edge processing is performed. If all the

corresponding modules are enabled, a total of 14 pixels per line (7 left most and 7 right most) and 8

lines (4 top most and 4 bottom most) will not be output.

• Simple horizontal averaging (by factors of 2, 4, or 8) to handle input widths that are greater than 1280

(plus the cropped number) pixels wide.

• Dark frame capture to DDR2.

• Dark frame subtraction for every input raw data frame, fetched from DDR2, pixel-by-pixel to improve

video quality.

• Lens shading compensation. Each input pixel is multiplied with a corresponding 8-bit gain value and

the result is right shifted by a programmable parameter (0-7 bits).

• A-law decompression to transform non-linear 8-bit data to 10-bit linear data. This feature allows data in

DDR2 to be 8-bits, which saves 50% of the area if the input to the preview engine is from the DDR2.

• Horizontal median filter for reducing temperature induced noise in pixels.

• Programmable noise filter that operates on a 3x3 grid of the same color (effectively, this is a five line

storage requirement).

• Digital gain and white balance (color separate gain for white balance).

• Programmable CFA interpolation that operates on a 5x5 grid.

• Conventional Bayer pattern RGB and complementary color sensors.

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