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6.9.4

DDR2 Memory Controller

6.9.4.1 DDR2 Memory Controller Electrical Data/Timing

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A

standard compliant DDR2 SDRAM Devices and can interface to either 16-bit or 32-bit DDR2 SDRAM

devices. For details on the DDR2 Memory Controller, see the TMS320DM643x DMP DDR2 Memory

Controller User’s Guide (literature number SPRU986).

DDR2 SDRAM plays a key role in a DaVinci-based system. Such a system is expected to require a

significant amount of high-speed external memory for:

• Buffering of input image data from sensors or video sources

• Intermediate buffering for processing/resizing of image data in the VPFE

• Numerous OSD display buffers

• Intermediate buffering for large raw Bayer data image files while performing image processing

functions

• Buffering for intermediate data while performing video encode and decode functions

• Storage of executable code for the DSP

A memory map of the DDR2 Memory Controller registers is shown in Table 6-26.

Table 6-26. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

ACRONYM

0x01C4 004C

DDRVTPER

DDR2 VTP Enable Register

0x01C4 2038

DDRVTPR

DDR2 VTP Register

0x2000 0000 - 0x2000 0003

Reserved

0x2000 0004

SDRSTAT

SDRAM Status Register

0x2000 0008

SDBCR

SDRAM Bank Configuration Register

0x2000 000C

SDRCR

SDRAM Refresh Control Register

0x2000 0010

SDTIMR

SDRAM Timing Register

0x2000 0014

SDTIMR2

SDRAM Timing Register 2

0x2000 0020

PBBPR

Peripheral Bus Burst Priority Register

0x2000 0024 - 0x2000 00BF

Reserved

0x2000 00C0

IRR

Interrupt Raw Register

0x2000 00C4

IMR

Interrupt Masked Register

0x2000 00C8

IMSR

Interrupt Mask Set Register

0x2000 00CC

IMCR

Interrupt Mask Clear Register

0x2000 00D0 - 0x2000 00E3

Reserved

0x2000 00E4

DDRPHYCR

DDR PHY Control Register

0x2000 00E8 - 0x2000 00EF

Reserved

0x2000 00F0

VTPIOCR

DDR VTP IO Control Register

0x2000 00F4 - 0x2000 7FFF

Reserved

The Implementing DDR2 PCB Layout on the TMS320DM643x DMP DMSoC Application Report (literature

number SPRAAL6) specifies a complete DDR2 interface solution for the DM6437 as well as a list of

compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all

DDR2 interface timings in this solution are met.

TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout

on the TMS320DM643x DMP DMSoC Application Report (literature number SPRAAL6).

Peripheral Information and Electrical Specifications

210

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