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TNETV1644ZDU6 Datasheet(PDF) 212 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 212 Page - Texas Instruments |
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212 / 306 page  6.10.1.1 CCD Controller (CCDC) TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 6-29. VPFE Register Address Range Descriptions (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C7 1000 – 0x01C7 13FF HIST VPFE – Histogram 0x01C7 1400 – 0x01C7 17FF H3A VPFE – Hardware 3A (Auto-Focus/WB/Exposure) 0x01C7 3400 – 0x01C7 3FFF VPSS VPSS Shared Buffer Logic Registers The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous formats from video decoder devices. The following features are supported by the CCDC module. • Conventional Bayer pattern format. • Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to an external timing generator. • Interface to progressive and interlaced sensors. • REC656/CCIR-656 standard (YCbCr 4:2:2 format, either 8- or 16-bit). • YCbCr 4:2:2 format, either 8- or 16-bit with discrete H and VSYNC signals. • Up to 16-bit input. • Optical black clamping signal generation. • Shutter signal control. • Digital clamping and black level compensation. • 10-bit to 8-bit A-law compression. • Low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output. • Output range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area). • Downsampling via programmable culling patterns. • Control output to the DDR2 via an external write enable signal. • Up to 16K pixels (image size) in both the horizontal and vertical direction. The CCDC register memory mapping is shown in Table 6-30. Table 6-30. CCDC Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0400 PID Peripheral Revision and Class Information 0x01C7 0404 PCR Peripheral Control Register 0x01C7 0408 SYN_MODE SYNC and Mode Set Register 0x01C7 040C HD_VD_WID HD and VD Signal Width 0x01C7 0410 PIX_LINES Number of Pixels in a Horizontal Line and Number of Lines in a Frame 0x01C7 0414 HORZ_INFO Horizontal Pixel Information 0x01C7 0418 VERT_START Vertical Line - Settings for the Starting Pixel 0x01C7 041C VERT_LINES Number of Vertical Lines 0x01C7 0420 CULLING Culling Information in Horizontal and Vertical Directions 0x01C7 0424 HSIZE_OFF Horizontal Size 0x01C7 0428 SDOFST SDRAM/DDRAM Line Offset 0x01C7 042C SDR_ADDR SDRAM Address 0x01C7 0430 CLAMP Optical Black Clamping Settings 0x01C7 0434 DCSUB DC Clamp 0x01C7 0438 COLPTN CCD Color Pattern 0x01C7 043C BLKCMP Black Compensation 0x01C7 0440 - Reserved 0x01C7 0444 - Reserved Peripheral Information and Electrical Specifications 212 Submit Documentation Feedback |
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