TNETV1644ZDU6 datasheet(194/306 Pages) TI1

194 / 306 page

6.7 Clock PLLs

6.7.1

PLL1 and PLL2

PLLPWR18

EMI Filter

+1.8 V

0.01 mF

DM643x

PLL2

PLL1

0.1 mF

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

There are two independently controlled PLLs on DM6437. PLL1 generates the frequencies required for the

DSP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2 interface

and the VPBE in certain modes. The recommended reference clock for both PLLs is the 27-MHz crystal

input.

Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLLPWR18). An

external EMI filter circuit must be added to PLLPWR18, as shown in Figure 6-11. The 1.8-V supply of the

EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins

(DVDDDR2). TI recommends EMI filter manufacturer Murata, part number NFM18CC222R1C3.

All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the device as

possible. For the best performance, TI recommends that all the PLL external components be on a single

side of the board without jumpers, switches, or components other than the ones shown in Figure 6-11. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C1, C2, and the EMI Filter).

Figure 6-11. PLL1 and PLL2 External Connection

The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,

see Section 6.7.4, Clock PLL Electrical Data/Timing (Input and Output Clocks).

There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating

frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers must be

configured not to exceed any of these constraints documented in this section (certain combinations of

external clock inputs, internal dividers, and PLL multiply ratios might not be supported). For these

constraints (ranges), see Table 6-14 through Table 6-16.

Table 6-14. PLL1 and PLL2 Multiplier Ranges

PLL MULTIPLIER (PLLM)

MIN

MAX

PLL1 Multiplier

x14

x30

PLL2 Multiplier

x14

x32

Peripheral Information and Electrical Specifications

194

Submit Documentation Feedback

TNETV1644ZDU6 Datasheet(PDF) 194 Page - Texas Instruments

TNETV1644ZDU6 Datasheet(HTML) 194 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL