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TNETV1644ZDU6 Datasheet(PDF) 197 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 197 Page - Texas Instruments |
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197 / 306 page  6.7.2 PLL Controller Register Description(s) TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 A summary of the PLL controller registers is shown in Table 6-18. For more details, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978). Table 6-18. PLL and Reset Controller Registers Memory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL1 Controller Registers 0x01C4 0800 PID Peripheral ID Register 0x01C4 08E4 RSTYPE Reset Type Register 0x01C4 0900 PLLCTL PLL Controller 1 PLL Control Register 0x01C4 0910 PLLM PLL Controller 1 PLL Multiplier Control Register 0x01C4 0918 PLLDIV1 PLL Controller 1 Divider 1 Register (SYSCLK1) 0x01C4 091C PLLDIV2 PLL Controller 1 Divider 2 Register (SYSCLK2) 0x01C4 0920 PLLDIV3 PLL Controller 1 Divider 3 Register (SYSCLK3) 0x01C4 0924 OSCDIV1 PLL Controller 1 Oscillator Divider 1 Register (OBSCLK) [CLKOUT0 pin] 0x01C4 0928 – Reserved 0x01C4 092C BPDIV PLL Controller 1 Bypass Divider Register (SYSCLKBP) 0x01C4 0938 PLLCMD PLL Controller 1 Command Register 0x01C4 093C PLLSTAT PLL Controller 1 Status Register (Shows PLLC1 Status) PLL Controller 1 Clock Align Control Register 0x01C4 0940 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 1 PLLDIV Divider Ratio Change Status Register 0x01C4 0944 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0948 CKEN PLL Controller 1 Clock Enable Control Register 0x01C4 094C CKSTAT PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx) 0x01C4 0950 SYSTAT PLL Controller 1 SYSCLK Status Register (Indicates SYSCLK on/off Status) 0x01C4 0960 – Reserved 0x01C4 0964 – Reserved PLL2 Controller Registers 0x01C4 0C00 PID Peripheral ID Register 0x01C4 0D00 PLLCTL PLL Controller 2 PLL Control Register 0x01C4 0D10 PLLM PLL Controller 2 PLL Multiplier Control Register 0x01C4 0D18 PLLDIV1 PLL Controller 2 Divider 1 Register (SYSCLK1) 0x01C4 0D1C PLLDIV2 PLL Controller 2 Divider 2 Register (SYSCLK2) 0x01C4 0D20 - 0x01C4 0D2C – Reserved 0x01C4 0D2C BPDIV PLL Controller 2 Bypass Divider Register (SYSCLKBP) 0x01C4 0D38 PLLCMD PLL Controller 2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller 2 Status Register (Shows PLLC2 Status) PLL Controller 2 Clock Align Control Register 0x01C4 0D40 ALNCTL (Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation) PLL Controller 2 PLLDIV Divider Ratio Change Status Register 0x01C4 0D44 DCHANGE (Indicates if SYSCLK Divide Ratio has Been Modified) 0x01C4 0D48 – Reserved 0x01C4 0D4C CKSTAT PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx) 0x01C4 0D50 SYSTAT PLL Controller 2 SYSCLK Status Register (Indicates SYSCLK on/off Status) 0x01C4 0D54 - 0x01C4 0FFF – Reserved Submit Documentation Feedback Peripheral Information and Electrical Specifications 197 |
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