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TNETV1644ZDU6 Datasheet(PDF) 191 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 191 Page - Texas Instruments |
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191 / 306 page  MXI POR RESET RESETOUT SYSCLKREFCLK (PLLC1) SYSCLK1 SYSCLK2 SYSCLK3 CLKOUT0 Bootand ConfigurationPins Config PowerSuppliesStable 1 4 5 2 3 PLL1Clock Div1Clock Div3Clock Div6Clock DrivenorHi-Z 8 6 DrivenorHi-Z Z+/LowGroup (Zlonger-to-low) Z+/HighGroup (Zlonger-to-high) ZGroup 8 DDR2ZGroup DDR2LowGroup DDR2HighGroup Z/HighGroup (Z-to-high) 7 Z/LowGroup (Z-to-low) 7 DrivenorHi-Z DrivenorHi-Z DrivenorHi-Z 6 6 6 6 6 8 Z+/InvalidGroup (Zlonger-to-invalid) 9 Invalid TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 A. Pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. For more details on what pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see Section 6.5.8, Pin Behaviors at Reset. Figure 6-8. Warm Reset (RESET) Timing(A) Submit Documentation Feedback Peripheral Information and Electrical Specifications 191 |
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