TNETV1644ZDU6 datasheet(188/306 Pages) TI1

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6.5.9

Reset Electrical Data/Timing

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

• EMIFA: These EMIFA signals are multiplexed with boot and configuration pins: EM_A[4], EM_A[2:0],

EM_BA[0], EM_BA[1]; therefore, they are forced 3-stated throughout RESETOUT.

–

Z+/Low Group: EM_A[4], EM_A[2:0]

–

Z+/High Group: EM_BA[0], EM_BA[1], EM_OE, EM_WE

–

Z+/Invalid Group: EM_D[7:0]

–

Z/Low Group: EM_A[21:5], EM_A[3], EM_R/W

–

Z/High Group: EM_CS2

–

Z Group: EM_WAIT/(RDY/BSY)

• DDR2 Memory Controller:

–

Clock Group: DDR_CLK, DDR_CLK

–

DDR2 Z Group: DDR_DQM[3:0], DDR_DQS[3:0], DDR_D[31:0]

–

DDR2 Low Group: DDR_CKE, DDR_BA[2:0], DDR_A[12:0]

–

DDR2 High Group: DDR_CS, DDR_WE, DDR_RAS, DDR_CAS

• PCI: All PCI pins behave according to Z Group.

• I2C: All I2C pins behave according to Z Group.

• JTAG: TDO, EMU0, and EMU1 pins behave according to Z Group. TCK, TDI, TMS, and TRST are

input-only pins.

• Clock: CLKOUT0

For more information on the pin behaviors during device-level global reset, see Figure 6-7 and Figure 6-8

in Section 6.5.9, Reset Electrical Data/Timing.

Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)

resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.

Table 6-11. Timing Requirements for Reset (see Figure 6-7 and Figure 6-8)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

tw(RESET)

Pulse duration, POR low or RESET low

12C(1)

Setup time, boot and configuration pins valid before POR high or RESET

tsu(CONFIG)

12C(1)

high(2)

Hold time, boot and configuration pins valid after POR high or RESET

th(CONFIG)

high(2)

(1)

C = 1/MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)

requirement.

(2)

For the list of boot and configuration pins, see Table 2-5, Boot Terminal Functions.

Table 6-12. Switching Characteristics Over Recommended Operating Conditions During Reset(1)

(see Figure 6-8)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

PARAMETER

UNIT

MIN

MAX

td(RSTH-RSTOUTH)

Delay time, POR high or RESET high to RESETOUT high

1900C

tw(PAUSE)

Pulse duration, SYSCLKs paused (low) before RESETOUT high

10C

td(RSTL-IV)

Delay time, POR low or RESET low to pins invalid

td(RSTH-V)

Delay time, POR high or RESET high to pins valid

td(RSTOUTH-V)

Delay time, RESETOUT high to pins valid

td(RSTOUTH-IV)

Delay time, RESETOUT high to pins invalid

12C

(1)

C = 1/CLKIN1 clock frequency in ns.

Peripheral Information and Electrical Specifications

188

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