TNETV1644ZDU6 datasheet(184/306 Pages) TI1

184 / 306 page

6.5.1.1 Usage of POR versus RESET Pins

6.5.1.2 Latching Boot and Configuration Pins

6.5.2

Warm Reset (RESET Pin)

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

–

The I/O pins are controlled by the default peripherals (default peripherals are determined by

PINMUX0 and PINMUX1 registers).

–

The clock and reset of each peripheral is determined by the default settings of the Power and Sleep

Controller (PSC).

–

The PLL Controllers are operating in PLL Bypass Mode.

–

The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).

After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the

Using the TMS320DM643x Bootloader Application Report (literature number SPRAAG0).

After the boot sequence, follow the software initialization sequence described in Section 3.8, Device

Initialization Sequence After Reset.

POR and RESET are independent resets.

If the device needs to go through a power-up cycle, POR (not RESET) must be used to fully reset the

device.

In functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation

for functional end-system is to use the POR pin for full device reset. If RESET pin is not needed, it can be

pulled inactive (high) via an external pullup resistor.

In a debug system, it is typically desirable to allow the reset of the device without crashing an emulation

session. In this case, the user can use the POR pin to achieve full device reset and use the RESET pin to

achieve a debug reset—which resets the entire device except emulation logic.

Internal to the chip, the two device reset pins RESET and POR are logically AND’d together only for the

purpose of latching device boot and configuration pins. The values on all device and boot configuration

pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from

low-to-high.

A Warm Reset is activated by driving the RESET pin active low. This resets everything in the device

except the emulation logic. An emulator session will stay alive during warm reset.

For more information on POR vs. RESET usage, see Section 6.5.1.1, Usage of POR versus RESET Pins

and Section 6.5.1.2, Latching Boot and Configuration Pins.

The following sequence must be followed during a Warm Reset:

1. Power supplies and input clock source should already be stable.

2. The RESET pin must be asserted (low) for a minimum of 12 MXI cycles.

Within the low period of the RESET pin, the following happens:

–

The reset signals flow to the entire chip resetting all the modules on chip, except the emulation

logic.

–

The PLL Controllers are reset thereby, switching back to PLL Bypass Mode and resetting all their

registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.

–

The RESETOUT pin becomes asserted (low), indicating the device is in reset.

3. The RESET pin may now be deasserted (driven high).

When the RESET pin is deasserted (high), the configuration pin values are latched and the PLL

Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are

still in PLL Bypass Mode. Other device initialization also begins.

4. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the

end of these 10 cycles, the RESETOUT pin is deasserted (driven high).

Peripheral Information and Electrical Specifications

184

Submit Documentation Feedback

TNETV1644ZDU6 Datasheet(PDF) 184 Page - Texas Instruments

TNETV1644ZDU6 Datasheet(HTML) 184 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL