TNETV1644ZDU6 datasheet(183/306 Pages) TI1

183 / 306 page

6.5 Reset

6.5.1

Power-on Reset (POR Pin)

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

The reset controller detects the different type of resets supported on the DM6437 device and manages the

distribution of those resets throughout the device.

The DM6437 device has several types of device-level global resets - power-on reset, warm reset, and

max reset. Table 6-10 explains further the types of reset, the reset initiator, and the effects of each reset

on the chip. See Section 6.5.9, Reset Electrical Data/Timing, for more information on the effects of each

reset on the PLL controllers and their clocks.

Table 6-10. Device-Level Global Reset Types

TYPE

INITIATOR

EFFECT(s)

POR pin

Global chip reset (Cold reset). Activates the POR signal on chip,

which resets the entire chip including the emulation logic.

Power-on Reset

The power-on reset (POR) pin must be driven low during power

(POR)

ramp of the device.

Device boot and configuration pin are latched.

Resets everything except for the emulation logic. Emulator stays

Warm Reset

RESET pin

alive during Warm Reset.

Device boot and configuration pin are latched.

Same as a Warm Reset, except the DM6437 device boot and

Max Reset

Emulator, WD Timer (Timer 2)

configuration pins are not re-latched.

In addition to device-level global resets, the PSC provides the capability to cause local resets to

peripherals and/or the CPU.

Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the

emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a

power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies

have reached their normal operating conditions. If an external 27-MHz oscillator is used on the MXI/CLKIN

pin, the source clock should also be running at the correct frequency prior to de-asserting the POR pin.

Note: A device power-up cycle is not required to initiate a Power-on Reset.

The following sequence must be followed during a Power-on Reset.

1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low).

2. Wait for the input clock source to be stable while keeping the POR pin asserted (low).

3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted

(low) for a minimum of 12 MXI cycles.

Within the low period of the POR pin, the following happens:

–

The reset signals flow to the entire chip (including the emulation logic), resetting the modules on

chip.

–

The PLL Controller clocks start at the frequency of the MXI clock. The clocks are propagated

throughout the chip to reset the chip synchronously. By default, both PLL1 and PLL2 are in reset

and unlocked. The PLL Controllers default to PLL Bypass Mode.

–

The RESETOUT pin stays asserted (low), indicating the device is in reset.

4. The POR pin may now be deasserted (driven high).

When the POR pin is deasserted (high), the configuration pin values are latched and the PLL

Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are

still in PLL Bypass Mode. Other device initialization also begins.

5. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the

end of these 10 cycles, the RESETOUT pin is deasserted (driven high).

At this point:

Submit Documentation Feedback

Peripheral Information and Electrical Specifications

183

TNETV1644ZDU6 Datasheet(PDF) 183 Page - Texas Instruments

TNETV1644ZDU6 Datasheet(HTML) 183 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL