TNETV2664FIBZWT datasheet(238/249 Pages) TI1

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TMS320C6424

SPRS347D – MARCH 2007 – REVISED DECEMBER 2009

www.ti.com

6.22 IEEE 1149.1 JTAG

The JTAG(3) interface is used for BSDL testing and emulation of the C6424 device.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or

exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by

TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

For maximum reliability, C6424 includes an internal pulldown (IPD) on the TRST pin to ensure that TRST

will always be asserted upon power up and the device's internal emulation logic will always be properly

initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG

controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary scan operations.

6.22.1

JTAG ID (JTAGID) Register Description(s)

Table 6-91. JTAG ID Register

HEX ADDRESS RANGE

ACRONYM

COMMENTS

Read-only. Provides 32-bit

0x01C4 0028

JTAGID

JTAG Identification Register

JTAG ID of the device.

(3)

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

C6424 device, the JTAG ID register resides at address location 0x01C4 0028. For the actual register bit

names and their associated bit field descriptions, see Figure 6-48 and Table 6-92.

31-28

27-12

11-1

VARIANT (4-Bit)

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

R-n

R-1011 0111 0010 0001

R-0000 0010 111

R-1

LEGEND: R = Read, W = Write, n = value at reset

Figure 6-48. JTAG ID (JTAGID) Register—0x01C4 0028

238

Peripheral Information and Electrical Specifications

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