TNETV1002IDZHK datasheet(51/102 Pages) TI1

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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

The following paragraph lists the typical IRQ sequence. The FIQ sequence is similar.

•

As the interrupt handler sees unmasked interrupt inputs go active, it sets the corresponding IT_REG bit.

•

At this time, there are three possible cases:

If the NEW_INT_AGR bit in the INT_CTRL_REG is set, a previous interrupt has not yet been

completely serviced, and the new interrupt cannot be sent to the MCU.

If NEW_INT_AGR is 0 and there is only one interrupt marked as active in the IT_REG, that interrupt

number is selected as the interrupt to be passed to the MCU. This selected interrupt number is stored

in SIR_IRQ_REG.

If NEW_INT_AGR is 0 and there are more than one interrupt marked as active in the IT_REG, the

interrupt handler selects the highest-priority interrupt based on ILR_IRQ_n register priority values

and, where priority values are identical, interrupt numbers. This selected interrupt number is stored in

SIR_IRQ_REG.

•

The interrupt is sent to the MCU via its IRQ port.

•

The MCU begins execution at the IRQ vector. MCU code reads SIR_IRQ_REG to determine which

interrupt source caused the interrupt. MCU code branches to the appropriate Interrupt Service Routine.

•

The MCU software must write a “1” to the INT_CTRL_REG register NEW_IRQ_AGR bit in order to reset

the IRQ output and SIR_IRQ_REG register. This enables the interrupt handler to send new interrupts to

the MCU via the IRQ signal.

MCU subsystem interrupt numbers are shown in Table 4--4.

Table 4--4. MCU Peripheral Interrupt Mapping

IRQ REQUEST

MCU INTERRUPT SOURCE

IRQ0

Watchdog TIMER0 interrupt

IRQ1

TIMER1 interrupt

IRQ2

TIMER2 interrupt

IRQ3

GPIO0 interrupt

IRQ4

Ethernet interface interrupt

IRQ5

KBGPIO(7:0) interrupt

IRQ6

UART interrupts

IRQ7

UART_IRDA interrupt

IRQ8

KBGPIO(15:8) interrupt

IRQ9

GPIO03

IRQ10

GPIO02

IRQ11

I2C interrupt

IRQ12

GPIO1 interrupt

IRQ13

SPI interrupt

IRQ14

GPIO(19:4) interrupt

IRQ15

API interrupt

4.4

MCU Power-Down Modes

The MCU can be shut down and awaken by setting the appropriate bit into the CLKM_REG and

WAKEUP_REG. It is the software’s responsibility to put the ARM_CLOCK in bypass or low-frequency mode

before the MCU is shut down. The MCU is woken by the first interrupt received from one of the peripherals.

The MCU subsystem peripherals can be individually shut down and awaken by setting the corresponding bits

in the CLKM_REG and WAKEUP_REG register. It is the software’s responsibility to power down or wake up

individual peripherals.

TNETV1002IDZHK Datasheet(PDF) 51 Page - Texas Instruments

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