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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

The 5471 DSP subsystem includes the DSP CPU core, a programmable phase-locked loop (PLL) for clock

generation, an interface to external parallel devices, a timer, 72K words of RAM, two multichannel buffered

serial interfaces, an interface to allow MCU access to part of the DSP subsystem memory map, and a JTAG

interface.

3.1.1 DSP Memory Space and Buses

The 5471 subsystem has multiple memory spaces and four parallel buses that allow you to access both

program and data simultaneously. Each of the four buses access different memory spaces for different

aspects of the DSP operation:

•

The DSP subsystem includes 72K words of on-chip RAM, as well as an extensive external memory range,

which can be used to interface to a variety of memory types or peripherals.

•

The program bus (PB) reads from program memory space, which contains the instructions to be

executed.

•

The write data bus (EB) writes into data memory space, which stores data used by the instructions and

tables eventually used in execution. It also writes into I/O memory space.

•

The two read data buses (CB and DB) read data from the data memory space and the DB data bus

accesses I/O memory space. The I/O memory space interfaces to external memory-mapped peripherals

and can serve as extra data storage space.

3.1.2 DSP Scan-Based Emulation Logic

The 5471 DSP subsystem includes a dedicated emulation port for in-circuit emulation. The emulation port is

accessed directly by the Texas Instruments (TI) extended development system (XDS) hardware emulator and

provides emulation.

3.2

DSP Memory

The 5471 device implements 72K words of on-chip RAM as follows:

•

40K words of program-space single-access RAM (SARAM)

•

16K words of data space dual-access RAM (DARAM)

•

16K words of data space single-access RAM (SARAM)

Each block of DARAM may perform up to two DSP accesses in one machine cycle. The DSP subsystem may

also perform multiple accesses to separate memory blocks in one machine cycle. After a “normal” reset, the

data-space RAM blocks in the addresses between 0x0000 and 0x7FFF are mapped into data memory space

only, and the program space RAM blocks between 0x06000 and 0x0FFFF are mapped only to program space.

The OVLY and DROM bits can affect this as shown in Figure 3--2 and Figure 3--3.

3.2.1 DSP On-Chip RAM

The DSP subsystem features 72K x 16-bit of on-chip RAM (two blocks of 8K x 16-bit DARAM and seven blocks

of 8K x 16-bit SARAM). The DSP CPU can perform two accesses to a DARAM in one machine cycle (two

reads in one cycle, or a read and a write in one cycle). It can also perform multiple accesses to separate

memory blocks in one machine cycle.

After reset, the lower address range of the program space is mapped to external memory, the lower address

range of the data space is mapped with on-chip RAM blocks. However, the OVLY bit in the PMST register

can be used to map these RAM blocks into both program and data space.

3.2.2 Normal Mode DSP Memory Map

The normal mode DSP subsystem provides the memory map shown in Figure 3--2. This is the memory map

that applies when the API boot mode feature is not enabled. The normal mode memory map applies any time

that DSP register BSCR[4] (ABMDIS) is 1, or when MCU register DSP_REG[9] (DSP_APIBN) is 1.

TNETV1002IDZHK Datasheet(PDF) 23 Page - Texas Instruments

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