CC1150-RTR1 datasheet(30/67 Pages) TI1

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FIFO_THR=13

TXFIFO

CC1150

SWRS037B – JANUARY 2006 – REVISED MARCH 2015

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Table 5-7. FIFO_THR Settings

and the Corresponding FIFO

Thresholds (continued)

BYTES in TX

FIFO_THR

FIFO

0111

1000

1001

1010

1011

1100

1101

1110

1111

The chip status byte that is available on the SO pin while transferring the SPI address contains the fill

grade of the TX FIFO. Section 5.5.1 contains more details on this.

The number of bytes in the TX FIFO can also be read from the TXBYTES.NUM_TXBYTES status register.

The 4-bit FIFOTHR.FIFO_THR setting is used to program the FIFO threshold point. Table 5-7 lists the 16

FIFO_THR settings and the corresponding thresholds for the TX FIFO.

Figure 5-14. Example of FIFO at Threshold

A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed

threshold. The flag is used to generate the FIFO status signals that can be viewed on the GDO pins (see

Section 5.17).

Figure 5-15 shows the number of bytes in the TX FIFO when the threshold flag toggles, in the case of

FIFO_THR=13. Figure 5-15 shows the flag as the FIFO is filled above the threshold, and then drained

below.

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