CC1150-RTR1 datasheet(29/67 Pages) TI1

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CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

The calibration takes a constant number of XOSC cycles; see Table 5-6 for timing details. When TX is

active, the chip will remain in the TX state until the current packet has been successfully transmitted. Then

the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are:

•

IDLE

•

FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX.

•

TX: Start sending preambles

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. Note

that if the radio goes from TX to IDLE by issuing an SIDLE strobe, the automatic calibration-when-going-

from-TX-to-IDLE will not be performed.

5.11.5 Timing

The radio controller controls most timing in CC1150, such as synthesizer calibration and PLL lock.

Table 5-6 shows timing in crystal clock cycles for key state transitions. Timing from IDLE to TX is

constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods.

Power on time and XOSC start-up times are variable, but within the limits stated in Section 4.7.

NOTE

In a frequency hopping spread spectrum or a multi-channel protocol, the calibration time can

be reduced from 721 µs to approximately 150 µs. This is explained in Section 5.19.2.

Table 5-6. State Transition Timing

DESCRIPTION

XOSC PERIODS

26 MHz CRYSTAL

Idle to TX/FSTXON, no calibration

2298

88.4 µs

Idle to TX/FSTXON, with calibration

≈ 21037

809 µs

TX to IDLE, no calibration

0.1 µs

TX to IDLE, including calibration

≈ 18739

721 µs

Manual calibration

≈ 18739

721 µs

5.12 Data FIFO

The CC1150 contains a 64 byte FIFO for data to be transmitted. The SPI interface is used for writing to

the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect

underflow in the TX FIFO.

When writing to the TX FIFO, it is the responsibility of the MCU to avoid TX FIFO overflow. This will not be

detected by the CC1150. A TX FIFO overflow will result in an error in the TX FIFO content.

Table 5-7. FIFO_THR Settings

and the Corresponding FIFO

Thresholds

BYTES in TX

FIFO_THR

FIFO

0000

0001

0010

0011

0100

0101

0110

Detailed Description

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