LTC2424CG datasheet(21/28 Pages) LINER

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LTC2424/LTC2428

APPLICATIONS INFORMATION

where CSADC remains LOW after detecting EOC = 0. This

situation is easily avoided by adding an external 10k pull-

up resistor to the SCK pin.

DIGITAL SIGNAL LEVELS

The LTC2424/LTC2428’s digital interface is easy to use.

Its digital inputs (FO, CSADC, CSMUX, CLK, DIN and SCK

in External SCK mode of operation) accept standard TTL/

CMOS logic levels and can tolerate edge rates as slow as

100

µs.However,someconsiderationsarerequiredtotake

advantage of exceptional accuracy and low supply current.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

In order to preserve the accuracy of the LTC2424/LTC2428,

it is very important to minimize the ground path imped-

ance which may appear in series with the input and/or

reference signal and to reduce the current which may flow

through this path. The ZSSET pin (Pin 6) should be con-

nected directly to the signal ground.

The power supply current during the conversion state

should be kept to a minimum. This is achieved by restrict-

ing the number of digital signal transitions occurring

during this period.

While a digital input signal is in the 0.5V to (VCC – 0.5V)

range, the CMOS input receiver draws additional current

from the power supply. It should be noted that, when any

one of the digital input signals (FO, CSADC, CSMUX, DIN,

CLK and SCK in External SCK mode of operation) is within

this range, the LTC2424/LTC2428 power supply current

may increase even if the signal in question is at a valid logic

level. For micropower operation and in order to minimize

the potential errors due to additional ground pin current,

it is recommended to drive all digital input signals to full

CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].

Severe ground pin current disturbances can also occur

due to the undershoot of fast digital input signals. Under-

shoot and overshoot can occur because of the imped-

ance mismatch at the converter pin when the transition

time of an external control signal is less than twice the

propagation delay from the driver to LTC2424/LTC2428.

For reference, on a regular FR-4 board, signal propaga-

tion velocity is approximately 183ps/inch for internal

traces and 170ps/inch for surface traces. Thus, a driver

generating a control signal with a minimum transition

time of 1ns must be connected to the converter pin

through a trace shorter than 2.5 inches. This problem

becomes particularly difficult when shared control lines

are used and multiple reflections may occur. The solution

is to carefully terminate all transmission lines close to

their characteristic impedance.

Parallel termination near the LTC2424/LTC2428 input

pins will eliminate this problem but will increase the driver

power dissipation. A series resistor between 27

Ωand56Ω

placed near the driver or near the LTC2424/LTC2428 pin

will also eliminate this problem without additional power

dissipation. The actual resistor value depends upon the

trace impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma

analog-to-digital converter are applied to a switched ca-

pacitor network. This network consists of capacitors switch-

ing between the analog input (ADCIN), ZSSET (Pin 6) and

the reference (FSSET). The result is small current spikes

seen at both ADCIN and VREF. A simplified input equivalent

circuit is shown in Figure 18.

The key to understanding the effects of this dynamic input

current is based on a simple first order RC time constant

model. Using the internal oscillator, the internal switched

capacitor network of the LTC2424/LTC2428 is clocked at

153,600Hz corresponding to a 6.5

µs sampling period.

Fourteen time constants are required each time a capacitor

is switched in order to achieve 1ppm settling accuracy.

Therefore, the equivalent time constant at VIN and VREF

should be less than 6.5

µs/14 = 460ns in order to achieve

1ppm accuracy.

Input Current (VIN)

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. If the

settling is incomplete, it does not degrade the linearity

performance of the device. It simply results in an offset/

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