LTC2424CG datasheet(10/28 Pages) LINER

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LTC2424/LTC2428

indicating a new conversion cycle has been initiated. This

bit serves as EOC (Bit 23) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the VIN pin is maintained within

the – 0.3V to (VCC + 0.3V) absolute maximum operating

range, a conversion result is generated for any input value

from – 0.125 • VREF to 1.125 • VREF. For input voltages

greater than 1.125 • VREF, the conversion result is clamped

to the value corresponding to 1.125 • VREF. For input

voltages below – 0.125 • VREF, the conversion result is

clamped to the value corresponding to – 0.125 • VREF.

Channel Selection

Typically, CSADC and CSMUX are tied together or CSADC

is inverted and drives CSMUX. SCK and CLK are tied

together and driven with a common clock signal. During

channel selection, CSMUX is HIGH. Data is shifted into the

DIN pin on the rising edge of CLK, see Figure 4. Table 3

shows the bit combinations for channel selection. In order

to enable the multiplexer output, CSMUX must be pulled

LOW. The multiplexer should be programmed after the

previous conversion is complete. In order to guarantee the

conversion is complete, the multiplexer addressing should

be delayed a minimum tCONV (approximately 133ms for a

60Hz notch) after the data out is read.

While the multiplexer is being programmed, the ADC is in

a low power sleep state. Once the MUX addressing is

complete, the data from the preceding conversion can be

read. A new conversion cycle is initiated following the data

read cycle with the analog input tied to the newly selected

channel.

APPLICATIONS INFORMATION

Bit 20 (forth output bit) is the extended input range (EXR)

indicator. If the input is within the normal input range

≤ VIN ≤ VREF, this bit is LOW. If the input is outside the

normal input range, VIN > VREF or VIN < 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2424/LTC2428 Status Bits

Bit 23

Bit 22

Bit 21

Bit 20

Input Range

EOC

DMY

SIG

EXR

VIN > VREF

011

0 < VIN ≤ VREF

010

VIN = 0+/0–

1/0

VIN < 0

001

Bit 19 (fifth output bit) is the most significant bit (MSB).

Bits 19-0 are the 20-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 4. Whenever CSADC is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

In order to shift the conversion result out of the device,

CSADC must first be driven LOW. EOC is seen at the SDO

pin of the device once CSADC is pulled LOW. EOC changes

real time from HIGH to LOW at the completion of a

conversion. This signal may be used as an interrupt for an

external microcontroller. Bit 23 (EOC) can be captured on

the first rising edge of SCK. Bit 22 is shifted out of the

device on the first falling edge of SCK. The final data bit (Bit

0) is shifted out on the falling edge of the 23rd SCK and

may be latched on the rising edge of the 24th SCK pulse.

On the falling edge of the 24th SCK pulse, SDO goes HIGH

CSADC

SCK

SDO

CONVERSION

SLEEP

8 (OPTIONAL)

EOC = 1

LAST 8 BITS ALWAYS 1

EOC = 0

DATA OUT

4 STATUS BITS 20 DATA BITS

DATA OUTPUT

24248 F03

CONVERSION

Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408

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