LTC2424CG datasheet(13/28 Pages) LINER

13 / 28 page

LTC2424/LTC2428

data rate with a 5V reference. The relationship between the

output data rate (ODR) and the frequency applied to the FO

pin (FO) is:

ODR = FO/20480

For output data rates up to 50 samples/second, the total

unadjusted error (TUE) is better than 16 bits, and better

than 12 bits at 100 samples/second. As shown in Figure 8,

for output data rates of 100 samples/second, the TUE is

better than 15 bits for VREF below 2.5V. Figure 9 shows an

unaveraged total unadjusted error for the LTC2424 or

LTC2428 operating at 100 samples/second with VREF =

2.5V. Figure 10 shows the same device operating with a 5V

reference and an output data rate of 7.5 samples/second.

Operation at Higher Data Output Rates

The LTC2424/LTC2428 typically operate with an internal

oscillator of 153.6kHz. This corresponds to a notch fre-

quency of 60Hz and an output rate of 7.5 samples/second.

The internal oscillator is enabled if the FO pin is logic LOW

(logic HIGH for a 50Hz notch). It is possible to drive the FO

pin with an external oscillator for higher data output rates.

As shown in Figure 6, an external clock of 2.048MHz

applied to the FO pin results in a notch frequency of 800Hz

with a data output rate of 100 samples/second.

Figure 7 shows the total unadjusted error (Offset Error +

Full-Scale Error + INL + DNL) as a function of the output

APPLICATIONS INFORMATION

OUTPUT RATE (SAMPLES/SEC)

128

160

12 BITS

13 BITS

14 BITS

16 BITS

24248 F07

100

192

224

256

VREF = 5V

150

Figure 7. Total Error vs Output Rate (VREF = 5V)

LTC2424

0.1

µF

HCO4

10pF

270pF

C8 5pF

R7 5k

R6 47k

R8 1k

10k

10 TVEN POT

SWITCH

R9 1k

24248 F06

GND

VCC

FSSET

ADCIN

ZSSET

GND

MUXOUT

VCC

CH0

CH1

CH2

CH3

GND

SCK

SDO

CSADC

GND

DIN

CSMUX

CLK

GND

Figure 6. Selectable 100 Sample/Second Turbo Mode

REFERENCE VOLTAGE (V)

1.0

128

192

5.0

24248 F08

2.0

3.0

4.0

1.5

2.5

3.5

4.5

256

160

224

OUTPUT RATE = 100sps

12 BITS

13 BITS

14 BITS

15 BITS

Figure 8. Total Error vs VREF (Output Rate = 100sps)

INPUT VOLTAGE (V)

–40

–30

–25

–20

–15

–10

–5

24248 F09

–35

2.5

VCC = 5V

VREF = 2.5V

Figure 9. Total Unadjusted Error at

100 Samples/Second (No Averaging)

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