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LTC1406IGN Datasheet(PDF) 6 Page - Linear Technology

No. de pieza LTC1406IGN
Descripción Electrónicos  Low Power, 8-Bit, 20Msps, Sampling A/D Converter
PDF  16 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC1406IGN Datasheet(HTML) 6 Page - Linear Technology

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6
LTC1406
PIN FUNCTIONS
AVDD (Pin 9): Analog 5V Positive Supply. Bypass to ana-
log ground plane with 10
µF tantalum in parallel with 0.1µF
or 10
µF ceramic.
AGND (Pin 10):Analog Ground. Tie to analog ground plane.
DGND (Pin 11): Digital Ground for Internal Logic. Tie to
analog ground plane.
DVDD(Pin12):Digital5VPositiveSupply.BypasstoDGND
with 10
µF tantalum in parallel with 0.1µF or 10µF ceramic.
NC (Pins 13, 14): No Internal Connection.
D7 to D0 (Pins 15 to 22): Digital Data Outputs. The out-
puts swing between OVDD and OGND.
OF/UF (Pin 23): Overflow/Underflow Bit. OF/UF high with
D7 to D0 all high indicates an overrange, OF/UF high with
D7 to D0 all low indicates an underrange condition. OF/UF
low indicates a conversion within the normal input range.
The outputs swing between OVDD and OGND.
CLK (Pin 24):Clock Input. Internal sample-and-hold tracks
the input signal when CLK is high and samples the input
signal on the falling edge.
AVDD = DVDD = VDD
NOMINAL (V)
ABSOLUTE MAXIMUM (V)
PIN
NAME
DESCRIPTION
MIN
TYP
MAX
MIN
MAX
1
OGND
Ground for Output Drivers
0
– 0.3
VDD + 0.3
2OVDD
Supply for Output Drivers
2.7
3 or 5
5.25
– 0.3
6
3
SHDN
Shutdown Input, Active Low
0
VDD
– 0.3
10
4VBIAS
Internal Bias Voltage
1.9
2.2
2.5
– 0.3
VDD + 0.3
5VREF
External Reference Input
2
2.5
3
– 0.3
VDD + 0.3
6
AGND
Analog Ground, Clean Ground
0
– 0.3
VDD + 0.3
7AIN+
Positive Analog Input,
±1V Span
0
VDD
– 0.3
VDD + 0.3
8AIN–
Negative Analog Input
0
VDD
– 0.3
VDD + 0.3
9AVDD
Analog Supply
4.75
5
5.25
– 0.3
6
10
AGND
Analog Ground, Substrate Ground
0
– 0.3
VDD + 0.3
11
DGND
Digital Ground
0
– 0.3
VDD + 0.3
12
DVDD
Digital Supply
4.75
5
5.25
– 0.3
6
13 to 14
NC
No Connect, No Internal Connection
15 to 22
D7 to D0
Data Outputs
OGND
OVDD
– 0.3
VDD + 0.3
23
OF/UF
Overflow/Underflow Output
OGND
OVDD
– 0.3
VDD + 0.3
24
CLK
Clock Input
0
VDD
– 0.3
10
TI I G DIAGRA
ANALOG
SIGNAL
CLOCK
N – 1
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
1406 TD
N
t6
N + 1
DATA OUT
t3
t1
t2
N + 2
N + 3
N + 4
N + 6
N + 5
t4
t5



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