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LTC1406IGN Datasheet(PDF) 5 Page - Linear Technology

No. de pieza LTC1406IGN
Descripción Electrónicos  Low Power, 8-Bit, 20Msps, Sampling A/D Converter
PDF  16 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC1406IGN Datasheet(HTML) 5 Page - Linear Technology

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LTC1406
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CODE
0
256
1406 G07
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
Supply Current vs
Sampling Frequency
SAMPLING FREQUENCY (Hz)
100k
35
30
25
20
15
10
5
0
1M
10M
1406 G09
20M
INPUT FREQUENCY (Hz)
100k
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G04
Intermodulation Distortion Plot
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1406 G05
0123
4
5
67
8
9
10
fSAMPLE = 20MHz
fIN1 = 3.500977MHz
fIN2 = 3.598633MHz
Differential Nonlinearity
vs Output Code
OUTPUT CODE
0
256
1406 G06
64
128
192
1.0
0.5
0
–0.5
–1.0
32
96
160
224
INPUT FREQUENCY (Hz)
100k
70
60
50
40
30
20
10
0
1M
10M
100M
1406 G08
Input Common Mode Rejection
vs Input Frequency
Integral Nonlinearity
vs Output Code
Spurious-Free Dynamic Range
vs Input Frequency
PIN FUNCTIONS
OGND (Pin 1): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 2): Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10
µF tantalum in parallel with 0.1µF or 10µF
ceramic.
SHDN (Pin 3): Power Shutdown Input. Logic low selects
shutdown.
VBIAS (Pin 4): Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10
µF tantalum in par-
allel with 0.1
µF or 10µF ceramic.
VREF (Pin 5): External 2.5V Reference Input. Bypass to
analog ground plane with 10
µF tantalum in parallel with
0.1
µF or 10µF ceramic.
AGND (Pin 6): Analog Ground. Tie to analog ground plane.
AIN+ (Pin 7): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN
+) – (AIN–)] = –1V.
AIN– (Pin 8): ±1V Input. The maximum output code
occurs when [(AIN+) – (AIN–)] = 1V. The minimum output
code occurs when [(AIN
+) – (AIN–)] = –1V. For single-
ended operation, tie AIN– to a DC voltage (e.g., VREF).



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